1. Field of the Invention
The present invention relates to a common memory protection system that is used in an apparatus having a multiprocessor configuration, and more particularly to a common memory protection system in which data stored in a common memory is prevented from being destroyed, when a faulty processor accesses the common memory.
2. Description of the Related Art
In a monitor control apparatus for radio communication, etc., which has a multiprocessor configuration, a random access memory (RAM) is used as a common memory that is accessed in common by a plurality of processors. The common RAM is used for a synchronizing operation between the processors and to store common data between them. The common RAM is periodically accessed by the processors, and thereby data stored in the RAM is rewritten.
In such an apparatus, even if a problem occurs in one operating processor, it is required that data stored in a common RAM is not destroyed when the faulty processor accesses the common RAM.
Conventionally, a semaphore-flag is used in order that when a CPU is writing data in a data area of the common RAM, other CPUs are allowed to only read data from the same data area, so that two CPUs do not simultaneously access the same data area for writing.
In the conventional use of semaphore-flags, a read-modify-write-cycle command, e.g., "TAS", "CAS", etc., is issued to execute read, write, or bit test operations of a certain address during one bus cycle. As for the hardware configuration thereof, commercial RAM is used for a predetermined amount of memory.
However, in a conventional common memory protection system, there is a problem in that if an error occurs in a part of an address bus buffer in a common bus when a CPU accesses a common RAM vir the common bus, the CPU may rewrite data to an incorrect area in the common RAM. This is because since the incorrect area accessed by the CPU is a part of an area of the common RAM, a semaphore-flag may be detected and thereby the common RAM can be accessed.
For example, it is assumed that a common RAM addresses with a 20-bit address bus (A0-A19) 00000h to FFFFFh in hexadecimal (h), and due to a problem, the output of an address line A 15 of an address buffer in a common bus is fixed to "1". In such a case, for example, if the CPU accesses 00000h, 08000h in the common RAM would actually be accessed by the CPU, and thereby, data that should not be changed may be destroyed.
In this case, there would be a problem in that it would be impossible to operate normally as a whole apparatus because of the data destroyed in the common RAM, even if CPUs other than a faulty CPU can operate normally.